These devices contain two independent positive-edge-triggered D-type flip-flops. A lowlevel at the preset (PRE) or clear (CLR) inputs setsor resets the outputs regardless of the levels of theother inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time ofCLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. The SN74ALS74A is characterizedfor operation from 0°C to 70°C.

Datasheet Available:Texas Instruments SN74ALS74A

SOIC 14 package. Manufactured by Texas Instruments.
G331S