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G12510 - 74F113 Dual J-K Negative Edge-Triggered Flip-Flop
The 74F113, dual negative edge-triggered JK-type flip-flop, features individual J, K, clock (CP), set (SD) inputs, true and complementary outputs. The asynchronous SD input, when low, forces the outputsto the steady state levels as shown in the function table regardless of the level at the other inputs. A high level on the clock (CP) input enables the J and K inputs anddata will be accepted. The logic levels at the J and K inputs may be allowed to change while the CP is high and flip-flop will perform according to the function table as long as minimum setup and hold times are observed. Output changes are initiated by the high-to-low transition of the CP.
14 pin DIP. Actual brand may vary from picture.
G12510
14 pin DIP. Actual brand may vary from picture.
G12510
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G12510 - 74F113 Dual J-K Negative Edge-Triggered Flip-Flop
G12510 - 74F113 Dual J-K Negative Edge-Triggered Flip-Flop
The 74F113, dual negative edge-triggered JK-type flip-flop, features individual J, K, clock (CP), set (SD) inputs, true and complementary outputs. The asynchronous SD input, when low, forces the outputsto the steady state levels as shown in the function table regardless of the level at the other inputs. A high level on the clock (CP) input enables the J and K inputs anddata will be accepted. The logic levels at the J and K inputs may be allowed to change while the CP is high and flip-flop will perform according to the function table as long as minimum setup and hold times are observed. Output changes are initiated by the high-to-low transition of the CP.
14 pin DIP. Actual brand may vary from picture.
G12510
14 pin DIP. Actual brand may vary from picture.
G12510
$0.16
Original: $0.45
-64%G12510 - 74F113 Dual J-K Negative Edge-Triggered Flip-Flop—
$0.45
$0.16Product Information
Product Information
Shipping & Returns
Shipping & Returns
Description
The 74F113, dual negative edge-triggered JK-type flip-flop, features individual J, K, clock (CP), set (SD) inputs, true and complementary outputs. The asynchronous SD input, when low, forces the outputsto the steady state levels as shown in the function table regardless of the level at the other inputs. A high level on the clock (CP) input enables the J and K inputs anddata will be accepted. The logic levels at the J and K inputs may be allowed to change while the CP is high and flip-flop will perform according to the function table as long as minimum setup and hold times are observed. Output changes are initiated by the high-to-low transition of the CP.
14 pin DIP. Actual brand may vary from picture.
G12510
14 pin DIP. Actual brand may vary from picture.
G12510
