The GAL16V8D-3LJ, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. GAL16V8D-3LJ devices are capable of emulating any of these PAL architectures with full function/fuse map/parametric compatibility. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, these devices deliver 100% field programmability and the functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.

Features:
3.5 ns Maximum Propagation Delay
Fmax = 250 MHz
3.0 ns Maximum from Clock Input to Data Output 50% to 75%
Reduction In Power From Bipolar
Active Pull-Ups On All Pins
Reconfigurable Logic
Reprogrammable Cells
100% Tested/100% Yields
High Speed Electrical Erasure (<100ms)
20 Year Data Retention
Maximum Flexibility for Complex Logic Designs
Programmable Output Polarity
Preload And Power-On Reset Of All Registers

Datasheet Available:Lattice GAL16V8D-3LJ

PLCC 20 package. Manufactured by Lattice Semiconductor Corp.
A20589